As described in the "How to run Media SDK samples on Skylake" post, at https://software.intel.com/en-us/forums/intel-media-sdk/topic/593838 , it is necessary to use 32-byte alignment for both the width and height when encoding using HEVC. Is there an expectation that this requirement will be relaxed in the future? This is a bit of a pain, since if we consider 720p, a frequently used progressive video format, a 720p video frame can be used unaltered with H.264 but the height must be aligned to 736 with HEVC, requiring the creation of an additional buffer.
Also, related to this, the following code in pipeline_encode.cpp pertains to HEVC:
// In case of HEVC when height and/or width divided with 8 but not divided with 16 // add extended parameter to increase performance if ( ( !((m_mfxEncParams.mfx.FrameInfo.CropW & 15 ) ^ 8 ) || !((m_mfxEncParams.mfx.FrameInfo.CropH & 15 ) ^ 8 ) ) && (m_mfxEncParams.mfx.CodecId == MFX_CODEC_HEVC) ) { m_ExtHEVCParam.PicWidthInLumaSamples = m_mfxEncParams.mfx.FrameInfo.CropW; m_ExtHEVCParam.PicHeightInLumaSamples = m_mfxEncParams.mfx.FrameInfo.CropH; m_EncExtParams.push_back((mfxExtBuffer*)&m_ExtHEVCParam); }
This code, however, preexisted the change described in the "How to run Media SDK samples on Skylake" post. Is this code snippet still relevant for Skylake HW HEVC encoding?